Principal Engineer, IP Enablement- Foundry Services
Job Details:
Job Description:
About Foundry ServicesAs an integral part of Intel's new IDM2.
0 strategy, we are establishing Foundry Services , a fully vertical, standalone foundry business, reporting directly to the CEO.
IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally.
Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and EuropeAbout the Role:
This job opportunity will be part of the Ecosystem Technology Office (ETO) group responsible for enabling IP ecosystem portfolio in support of Intel IDM2.
0 strategy and IFS customers.
The candidate will need to work with Ecosystem IP partners and IFS stakeholders to develop a rich and competitive IP portfolio for the foundry platform on leading-edge foundry technologies to enable customer products and address market segments with best-in-class PPAC - power, performance, area, cost IPs.
The candidate will be the IP Technical lead and the primary technical point of contact between Intel IFS, and IP ecosystem partners who are designing silicon IP to support multiple Intel process technologies.
In this position you will play a key technical leadership role in IP design.
The selected candidate for this position will be responsible for but not limited to:
Synthesize IP requirements into technical specifications that are best in class for PPAC.
Familiar with detailed IP specification and architecture to drive RFI, RFQ and SoW process with IP partners.
Demonstrate deep technical knowledge of Mixed Signal & High-Speed IPs based on past or present hands-on experience.
Drive technical support for IFS Ecosystem IP development programs during IP lifecycle:
High Speed Serdes IP PCIe, Ethernet, D2D IP-UCIe, AIB Memory I/F DDR, LPDDR, HBM- Mixed Signal IP's - ADC, DAC, PLL- and Foundational IP Embedded memories, Logic Libraries, GPIO.
Demonstrate ability to collaborate, influence and drive decisions in a cross-functional setting.
Partner with IFS teams as a subject matter expert to facilitate IP development through IP ecosystem partners.
Work closely with IP ecosystem partners and IFS teams on defining spec and developing IPs for IFS customers, following industrial IP development process.
Primary technical interface to 3rd party IP Partners and cross functional teams.
Collaborate with IFS stakeholder to Technology Development to resolve technology limitation and issues during IP planning and early development stage.
Engage in Technical Evaluation, AMS Design Technology Co-Optimization (DTCO), and Embedded Memory and Logic library Process IP Co-Optimization (PICO) activities with IP partners to ensure good collaboration and technical discussion on potential process improvements.
Lead IP Design reviews and IP Quality Assurance (QA) audits.
Review Test Chip validation plans, characterization reports, to ensure developed IP is compliant to spec.
Participate in industry standard consortiums and contribute to IP RoadmapThe ideal candidate should exhibit the following behavioral traits:
Experience as a technical lead; ability to communicate effectively, collaborate, and build long-term relationships across the organization.
Exceptional problem-solving abilities and repertoire of skillsAnalytical skills and experience formulating clear partner and technology strategies with cross-functional teams.
Proven experience influencing cross-functional teams.
Drive velocity of technical execution and thrive in solving complex problems for IP partners and customer.
Service mindset with a focus on quality solutions.
Skills with ecosystem partnership collaborations.
Strong communication and presentation skills to executive management.
Fearless mindset for growth and passion for continuous learningCommitted to encouraging an open and inclusive work environment.
Experience and SkillsAdvanced knowledge of IP development process, design trade-off, tools/flows, verification, and methodologies and life cycle in an SoC Customer and 3rd party IP vendors engagement and support in a technical capacity.
Demonstrated E2E IP design - spec definition, IP circuit and layout, designed using industry standard tools for pre- and post-Si validation and participated in integration of IP into a SOC for a successful HVM.
Deep understanding of design specifications and requirements in building Mixed Signal IPs.
Specification knowledge of IP standards (DDR/LPDDR/HBM, USB, MIPI, PCIe, USB, HDMI) and usage per market segment.
Experience on high-speed interface controller and/or PHY verificationKnowledge of AXI, PIPE and DFI interface protocols
Qualifications:
Master's degree with 7
years of experience listed below, or a PhD with 3
years of experience listed below, in Electrical Engineering7
years of experience in designing High Speed/ Analog/Mixed Signal IPs on leading edge technologies.
5
years of experience in technical problem solving.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, FolsomAdditional Locations:
US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:
Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs.
With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of TrustThis role is a Position of Trust.
Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks.
For internals, this investigation may or may not be completed prior to starting the position.
For additional questions, please contact your Recruiter.
Benefits:
We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California:
$186,760.
00-$299,166.
00Salary range dependent on a number of factors including location and experience.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
SummaryLocation:
US, California, Folsom; US, Oregon, Hillsboro; US, California, Santa Clara; US, Texas, Austin; US, Arizona, PhoenixType:
Full time.
Estimated Salary: $20 to $28 per hour based on qualifications.
Job Description:
About Foundry ServicesAs an integral part of Intel's new IDM2.
0 strategy, we are establishing Foundry Services , a fully vertical, standalone foundry business, reporting directly to the CEO.
IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally.
Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and EuropeAbout the Role:
This job opportunity will be part of the Ecosystem Technology Office (ETO) group responsible for enabling IP ecosystem portfolio in support of Intel IDM2.
0 strategy and IFS customers.
The candidate will need to work with Ecosystem IP partners and IFS stakeholders to develop a rich and competitive IP portfolio for the foundry platform on leading-edge foundry technologies to enable customer products and address market segments with best-in-class PPAC - power, performance, area, cost IPs.
The candidate will be the IP Technical lead and the primary technical point of contact between Intel IFS, and IP ecosystem partners who are designing silicon IP to support multiple Intel process technologies.
In this position you will play a key technical leadership role in IP design.
The selected candidate for this position will be responsible for but not limited to:
Synthesize IP requirements into technical specifications that are best in class for PPAC.
Familiar with detailed IP specification and architecture to drive RFI, RFQ and SoW process with IP partners.
Demonstrate deep technical knowledge of Mixed Signal & High-Speed IPs based on past or present hands-on experience.
Drive technical support for IFS Ecosystem IP development programs during IP lifecycle:
High Speed Serdes IP PCIe, Ethernet, D2D IP-UCIe, AIB Memory I/F DDR, LPDDR, HBM- Mixed Signal IP's - ADC, DAC, PLL- and Foundational IP Embedded memories, Logic Libraries, GPIO.
Demonstrate ability to collaborate, influence and drive decisions in a cross-functional setting.
Partner with IFS teams as a subject matter expert to facilitate IP development through IP ecosystem partners.
Work closely with IP ecosystem partners and IFS teams on defining spec and developing IPs for IFS customers, following industrial IP development process.
Primary technical interface to 3rd party IP Partners and cross functional teams.
Collaborate with IFS stakeholder to Technology Development to resolve technology limitation and issues during IP planning and early development stage.
Engage in Technical Evaluation, AMS Design Technology Co-Optimization (DTCO), and Embedded Memory and Logic library Process IP Co-Optimization (PICO) activities with IP partners to ensure good collaboration and technical discussion on potential process improvements.
Lead IP Design reviews and IP Quality Assurance (QA) audits.
Review Test Chip validation plans, characterization reports, to ensure developed IP is compliant to spec.
Participate in industry standard consortiums and contribute to IP RoadmapThe ideal candidate should exhibit the following behavioral traits:
Experience as a technical lead; ability to communicate effectively, collaborate, and build long-term relationships across the organization.
Exceptional problem-solving abilities and repertoire of skillsAnalytical skills and experience formulating clear partner and technology strategies with cross-functional teams.
Proven experience influencing cross-functional teams.
Drive velocity of technical execution and thrive in solving complex problems for IP partners and customer.
Service mindset with a focus on quality solutions.
Skills with ecosystem partnership collaborations.
Strong communication and presentation skills to executive management.
Fearless mindset for growth and passion for continuous learningCommitted to encouraging an open and inclusive work environment.
Experience and SkillsAdvanced knowledge of IP development process, design trade-off, tools/flows, verification, and methodologies and life cycle in an SoC Customer and 3rd party IP vendors engagement and support in a technical capacity.
Demonstrated E2E IP design - spec definition, IP circuit and layout, designed using industry standard tools for pre- and post-Si validation and participated in integration of IP into a SOC for a successful HVM.
Deep understanding of design specifications and requirements in building Mixed Signal IPs.
Specification knowledge of IP standards (DDR/LPDDR/HBM, USB, MIPI, PCIe, USB, HDMI) and usage per market segment.
Experience on high-speed interface controller and/or PHY verificationKnowledge of AXI, PIPE and DFI interface protocols
Qualifications:
Master's degree with 7
years of experience listed below, or a PhD with 3
years of experience listed below, in Electrical Engineering7
years of experience in designing High Speed/ Analog/Mixed Signal IPs on leading edge technologies.
5
years of experience in technical problem solving.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, FolsomAdditional Locations:
US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:
Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs.
With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of TrustThis role is a Position of Trust.
Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks.
For internals, this investigation may or may not be completed prior to starting the position.
For additional questions, please contact your Recruiter.
Benefits:
We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California:
$186,760.
00-$299,166.
00Salary range dependent on a number of factors including location and experience.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
SummaryLocation:
US, California, Folsom; US, Oregon, Hillsboro; US, California, Santa Clara; US, Texas, Austin; US, Arizona, PhoenixType:
Full time.
Estimated Salary: $20 to $28 per hour based on qualifications.
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